Effect of gate voltage variations on the carrier density in quantum well channel SISFET structures

A novel variant on the basic SISFET (semiconductor-insulator-semiconductor FET), likely to have improved performance, involves using a second wide bandgap layer to form a rectangular quantum well channel. In particular, the second barrier would help to improve carrier confinement by reducing hot carrier injection into the substrate at the drain end of the gate. In this paper the results of a study of the effect of gate bias on the electron density in n-channel quantum well SISFET structures are presented. Calculations of the electron densities induced in the SISFET channel by different gate voltages have been performed by solving Poisson's Equation together with the one-dimensional, time independent Schrodinger Equation so that the gate voltage range for n-channel enhancement mode operation can be identified. The basic quantum well SISFET structure investigated is shown. The modelling is facilitated by treating the gate contact semiconductor layer as a metal having a Schottky barrier of the same height as the heterostructure band offset between the gate contact and gate barrier layers. As a second simplification, the wave function penetration into the barriers is assumed to follow a exponential decay with depth from the quantum well, with the boundary condition of zero wave function amplitude at the interface between the top barrier and the gate contact layer. In addition exchange-correlation effects have been neglected in Schrodinger's equation. The dielectric constant is assumed invariant through the structure, which is reasonable for In/sub x/Ga/sub 1-x/As/Al/sub y/Ga/sub 1-y/As heterojunction FETs considered here.<
>