A 0.8 mu m CMOS technology for high performance ASIC memory and channelless gate array

A generic 0.8- mu m, polycide-gate, double-layer metal CMOS technology with twelve masking steps for next-generation memories and gate arrays has been developed. Key design rules and technology features are given. An I-line stepper is used for fine line definition down to the 0.7- mu m region. The technology has been demonstrated with a full CMOS 16 K SRAM (static random-access memory) circuit. POP-SILO isolation, 175-A gate oxide, Ta polycide gate material, halo LDD (lightly doped drain) n and p devices, TiN/TiSi/sub 2/ contact and barrier metal, partial etchback SOG (spin-on-glass) planarization, and Al/Ti metal systems provide high performance and reliable process technology.<
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