Recent progress in synthesis for testability

Describes recent work involving the automatic synthesis of VLSI circuits with testability considerations. The first put of this paper explores the potential for logic synthesis to allow designers to more comprehensively test circuits while simultaneously diminishing the need for fault simulation and automatic test pattern generation. Logic optimization procedures can be used to produce circuits that are completely testable for single stuck-at faults. Testing for faults such as multiple stuck-at faults, gate delay faults and path delay faults is a greater challenge, but logic synthesis and optimization procedures can produce circuits that have high degrees of testability under these models as well. For each of these fault models test vectors can be produced as a by-product of the synthesis process and vector minimization algorithms can be used in the place of fault simulation to reduce the size of the test vector sets. The second part of the paper considers the difficult problem of synthesizing sequential circuits with high degrees of single stuck-at fault coverage without incurring the area and performance penalty of scan registers. Initial results at combining synthesis for testability approaches with register-transfer level automatic test-pattern generation to produce vector sets that give complete single stuck-at fault coverage without the use of scan.<
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