Verifying ASICs by symbolic simulation

A new tool which is capable of dealing with digital circuit designs on a functional, or behavioural, level is presented. The tool has been used extensively in a design center for ASICS, and several real-life applications of it are described. The basis of the new tool is formed by efficient algorithms for manipulating Boolean functions and finite-state machines. Among the applications of the tool are automatic formal verification of combinatorial and sequential circuits, reverse engineering, (e.g. generation of state transition tables from circuit designs), rapid prototyping. validation of new CAD tools, verification of hand optimizations of tool-generated circuits and algorithm design.<
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