An ASIC RISC-based I/O processor for computer applications

Describes a hard disk controller application and the RISC-based ISA Bus coprocessor called the I/O processor (IOP) from which the hard disk application was developed. The IOP is used as a central element in ISA (Industry Standard Architecture)-based peripheral controller applications. In this specific application, it incorporates a comprehensive set of function blocks in addition to the core 32-bit RISC processor. These include an ISA address decoder, a register file compatible with the PC/AT-compatible hard disk controller, a DRAM controller capable of support 16 M bytes of 32-bit memory, an interrupt controller, a DMA controller, a 2 K-byte ROM and a 512-byte RAM. The IOP has been optimized for application requiring high data transfer rates. Burst data transfers up to 40 M bytes per second may be attained with the RISC processor running at 10 MHz. A paging and interleaving DRAM controller is utilized so that slower DRAMs with 100 nanoseconds access times can be used.<
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