A four-transistor four-quadrant analog multiplier using MOS transistors operating in the saturation region

A four-quadrant analog multiplier using only four MOS transistors is presented. It is based on the square-law characteristic of a MOS transistor operating in the saturation region. Experimental results, obtained with a test circuit built with discrete devices and showing a linearity as high at 0.25% and bandwidths up to 28 and 40 MHz for both inputs, are presented.<
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