A cyclic charge-balancing A/D converter with capacitor mismatch error compensation

An algorithm is proposed for improving the speed of a charge-balancing analog-to-digital converter implemented by a switched-capacitor technique. The number of charge transfer operations required for a conversion is reduced. For example, the conversion rate in 16-b conversion is improved more than 128 times as compared to a conventional charge-balancing analog-to-digital converter. A compensation algorithm for the capacitor mismatch error is also proposed. The results of prototype experiments indicate that the maximum integral nonlinearity error is reduced to less than 0.04 LSB in 6-b conversion.<
>