A scaling procedure for Domino CMOS logic

The area required by domino CMOS gates to support a specific response-time performance and capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI Domino CMOS gates. The scaling procedure has resulted in scaled NFET widths very close to those obtained by Monte Carlo techniques and SPICE.<
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