An integrated approach to real-time pattern recognition

This paper details the architecture and design of a VLSI CMOS retina dedicated to very fast pattern recognition. The implementation of the recognition algorithms into silicon are detailed. The performances of the ixj pixel retina are evaluated for various input pattern sizes. A 64*32 pixel integrated circuit design is presented which performs a pattern recognition and localisation in less than 100 mu s. The application considered is character recognition.<
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