A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistors

A cell structure using poly Si TFTs (thin film transistors) to realize half-micron channel length, channel width, and isolation space is described. This structure also reduces the drain capacitance relative to conventional structures with cells fabricated on Si substrate with channel doping. A fully-self-aligned polySi TFT cell process sequence without complex SOI technologies such as SIMOX or laser recrystallization is developed. A study of the read-out operation indicates that the application of the TFT cells for EPROMs and flash memories is advantageous not only for access time improvement but also for cell scalability.<
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