A 3.3 V operation nonvolatile memory cell technology

The design and performance of a stacked-gate nonvolatile memory (EPROM/flash) cell operated with a 3.3-V/sub cc/ power supply are discussed. It is shown that optimally redesigned 5-V cells with thinner gate oxide reduced V/sub t/, and greater channel width can be operated on a 3.3-V V/sub cc/ should also be applicable to the next generation of 64-Mb devices and beyond.<
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