A 9 ns 4 Mb BiCMOS SRAM with 3.3 V operation

A description is given of a 4-Mb TTL (transistor-transistor logic) SRAM in 0.5- mu m BiCMOS technology which uses scaled-down features of optimized MOS and bipolar transistors and BinMOS circuits to achieve 9 ns access and low-power 3.3-V operation of a 16-b organization. The SRAM block diagram is presented, and the 0.5- mu m triple-polysilicon and double-metal BiCMOS process is summarized.<
>