A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure

An experimental 4-Mb flash EEPROM realizes 5-V-only operation by introducing a compact row decoder with a triple-well structure. Since the cell-source voltage during erase is only 5 V, high source-junction breakdown voltage is not necessary, making a smaller cell feasible. By optimizing memory cell implant, fast programming is achieved with 5 V drain voltage. A simple stable EEPROM redundancy circuit reduces chip test cost and has minimum effect on chip size compared with a polysilicon redundancy circuit. The chip is packaged in a 48-spin cerdip.<
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