Si-gate CMOS devices on a Si lateral solid-phase epitaxial layer

Si-gate CMOS devices fabricated on a lateral solid-phase epitaxial Si layer grown from vacuum-deposited amorphous Si over SiO/sub 2/ patterns are discussed. Electrical characteristics are examined and correlated with microstructural characteristics of the layer by performing transmission electron microscopy on actual transistors. The layer can be divided into three regions. Carrier mobilities obtained from each region are discussed in terms of the crystalline quality. The maximum obtained field-effect mobilities are 570 cm/sup 2//V-s and 160 cm/sup 2//V-s for n-channel and p-channel transistors, respectively. The SMOS inverter chain with 100 stages and a channel length of 1.5 mu m has a delay time of 310 ps per gate. These results indicate that the lateral solid-phase epitaxy has potential for the fabrication of high-speed silicon-on-insulator devices.<
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