Behavioral models of ASIC VLSI cells

Behavioral models, while more difficult to produce than gate-level models, provide invaluable features during the design verification process. These models exhibit timing and functional accuracy, while providing significantly increased performance and debug features. Techniques to decrease the effort required to produce behavioral models of ASIC VLSI cells are discussed. Behavioral models of ASIC VLSI cells can greatly decrease the time required to verify a design.<>