Circuit comparison by hierarchical pattern matching

The authors present a novel approach to circuit comparison and building-block recognition. In contrast to conventional systems, netlist pattern matching is employed as the basic principle, making it possible to identify arbitrary subcircuits in larger circuits. Typically, a hierarchical netlist derived from a schematic and a flat netlist extracted from a layout have to be compared. In the present approach, this is accomplished by the successive (bottom up) matching of the schematic cells in the layout netlist, thus restoring the schematic hierarchy. The pattern matching algorithm is embedded in a sophisticated hierarchy handling scheme, making it possible to process even ill-structured hierarchies. The method is independent of circuit technology and design style. Typical drawbacks of traditional systems such as the handling of parallel paths or the permutability of (groups of) terminals are overcome in a quite natural way. Additionally, the proposed approach offers a universal and flexible solution to the problem of functional but not too topological isomorphic subcircuits. Real-life examples prove its suitability in function and performance.<
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