Parallel test pattern generation using Boolean satisfiability

Recently, Larrabee proposed a sequential test generation algorithm for combinational circuits based on Boolean satisfiability and presented results on benchmark circuits in support of the viability of this approach. Parallel implementations of test generation algorithms are attractive in view of the known difficulty (NP-completeness) of the problem. This paper suggests parallel versions of Larrabee's algorithm, suitable for implementation on shared-memory and message-passing multicomputers.<
>