A dynamically reconfigurable parallel pipelined system for real-time image processing applications

An architecture of a dynamically reconfigurable, multidimensional multidirectional parallel pipelined (M/sup 2/P/sup 2/) system is presented for real time image processing applications. It is implemented as a chain of interconnected modules, each having high performance TMS320c25 processing elements (PEs). These PEs can be configured to operate as independent stages of a single pipeline or grouped into two or four multiprocessor pipeline stages. Also, different stages need not comprise an equal number of PEs. Rather, each stage is configured according to the processing requirement of that stage. This results in a highly efficient pipeline structure having optimum task division. The configuration of pipeline stages can be done under software control.<
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