A massively parallel systolic array processor system

The design of a massively parallel processor, comprised of 2304-bit-serial processor elements arranged in a 48 by 48 systolic array, is described. The system consists of the processor array, a microstore controller, and a host computer interface. Program development tools are available on the host computer. The processor array uses 32 NCR GAPP (Geometric Arithmetic Parallel Processor) microprocessor chips, while the microstore controller is implemented with a TMS32010 DSP chip and TTL (transistor-transistor logic) circuitry. Utilizing the nearest neighbor communication capabilities of the GAPP, the array receives data from the host at the south end of the array, outputs data to the host at the north edge of the array, and can wrap data between either the east and west or north and south edges. The array can also be configured as a linear array of 2304 processor elements. The microstore controller interfaces with the host and facilitates downloading of GAPP array machine code, provides for the debugging and monitoring of GAPP array execution from the host, and implements user-defined instructions.<
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