Application of a two-layer planarization process to VLSI intermetal dielectric and trench isolation processes

The application of a novel planarization process using a sacrificial fill layer of photoresist is presented. The process is shown to solve the planarization problems encountered in both intermetal dielectric for a 1.2 mu m 256 K SRAM technology and trench isolation for a0.8- mu m 1M SRAM technology. The process is a simple extension of the standard dielectric etch-back scheme. A discussion of how to precisely quantify circuit planarization using well-known techniques is also presented. This information can then be adapted for statistical quality control purposes.<
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