Analysis and optimization of BiCMOS gate circuits

An optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed whose parameters can be extracted with SPICE simulations. Therefore a device model can be precise, while keeping the optimization procedure simple and unchangeable in any device generation. With the proposed procedure, BiCMOS gate delays can be calculated quickly and optimized efficiently just by looking up design tables that are obtained easily and are applicable to any design with the same device technology. The sizing strategy of cascaded drivers is also studied. BiCMOS-BiCMOS cascaded buffers are optimized when the scale-up factor is e/sup 2.3/, while BiCMOS-CMOS cascaded buffers become the fastest when the scale-up factor, e/sup 1.6/, is employed. The strategy was successfully applied to the design of high-speed BiCMOS static-RAM (SRAM) macros for standard cell libraries.<
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