A neural network controller for a high-speed packet switch

A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented. In this switch, each input maintains a separate queue for each of the outputs, thus n/sup 2/ input queues in a (n*n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. A neural network maximizing the throughput of this switch is determined, and the energy function, its optimized parameters, and the connection matrix are given. Comparison of simulations with analytically derived upper and lower bounds shows close to optimal throughput. It is shown that this neural network may be implemented with existing technology for medium switch sizes.<
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