Quantitative analysis of mask misalignment and its effect on device performance

Mask misalignment associated with contact photolithography fabrication of discrete field-effect transistors (FETs) and monolithic microwave integrated circuits (MMICs) is quantified using three different approaches: FET source and drain resistance measurements, electrical measurement on potentiometer-like test structures, and scanning electron microscope (SEM) examination. The results indicate that, for the current process technology, the FET source and drain resistance measurement is the preferred approach for routine production control of misalignment. The error is typically within 0.1 mu m. Using automated laboratory equipment, a single wafer can be tested in less than 30 min with most of the time spent on equipment setup and data analysis. The actual measurement takes less than 1 s per FET to complete. Often the source and drain resistance data already exist as part of a DC FET screening test routine. The SEM examination, although time consuming, should be done periodically for calibration purposes.<
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