A systolic realization for 2-D digital filters

Systolic hardware realizations for two-dimensional finite-impulse-response (FIR) and infinite-impulse-response (IIR) digital filters are presented. The structure permits the 2-D input data to be scanned row-wise and broadcasted one value at a time to various processing elements. Shift registers are used to store the required data needed by the 2-D recursive equation. A processing element can be implemented in VLSI, and as many of these as are required to satisfy the order of the filter can be used to build the total structure.<
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