An algorithm for quadrisection and its application to standard cell placement

An efficient heuristic for hypergraph quadrisection is presented. A placement technique for standard cells based on quadrisection is also discussed in detail. Results show this method to be much superior to min-cut bisection, yielding improvements of up to 20% in area. It also compares favorably with simulated annealing, yielding improvements in area for most of the circuits under test. The placer runs about 100 times faster than a simulated-annealing based placement package.<>