Optimizing adders for WSI

The authors report on the speed and dynamic power dissipation of CMOS implementations of six different adders. The adders are constructed with inverters and two-to-four-input AND and OR gates. A figure of merit is presented that can be used to compare the adders based on their delay and relative dynamic power consumption. This figure of merit provides a common ground for ranking the adders in terms of their utility for WSI (wafer scale integration) applications. Extensive simulation was used to evaluate the switching characteristics, and the results are used to rank the adders in terms of speed, size, and the number of logic transitions (a measure of the dynamic power consumption for static CMOS circuits). According to the figure of merit, the carry lookahead adder is the best design for word sizes between 16 and 64 bits, inclusive.<
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