Simulation of Nanoscale Round-Top-Gate Bulk FinFETs with Optimal Geometry Aspect Ratio

In this paper, we explore electrical characteristics of a 25 nm round-top-gate FinFET on both bulk silicon and SOI substrates. Assuming an ideal fin angle Θ = 90°, device performance of the FinFET with doped and undoped channels are simulated with a three-dimensional quantum correction transport model. Theoretical comparison shows that undoped bulk FinFETs possess promising electrical characteristics among different structures. Effect of non-ideal fin angle and fin height on device performance is investigated in terms of different short-channel effects. Optimal configuration of structure for the 25 nm round-top-gate bulk FinFETs is drawn to show the strategy of fabrication in nanoscale CMOS devices.