Triple matrix product architectures for fast signal processing

A procedure is introduced to determine highly concurrent representation of linear algorithms. The technique replaces matrix/vector operations by sums of small-size triple matrix products. A specially dedicated array architecture performs each triple product without intermediate I/O operations. The highly concurrent representation is shown to be possible for any linear algorithm. The special architecture features dual-mode operation for processing elements and closed-loop data circulation. Both characteristics increase the flexibility and speed of the configuration.<
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