Probabilistic Testability Measure Before Pseudorandom Test Generation

It is proposed more suitable method of the testability analysis of the digital systems in comparison with known classical algorithmic and probabilistic methods. It is oriented on the complex combinational and sequential asynchronous logic circuits. Estimation of the testability is based on the topological analysis of the circuit. The new method and above mentioned methods were approved on the circuits of different complexity, including circuits from ISCAS'85, '89 Libraries. Proposed method can be used on gate-level and RT-level circuit description