A 0.9-V 96-/spl mu/W Digital Hearing Aid Chip with Heterogeneous S-D DAC

A full chip implementation of a low-power digital hearing aid is reported. It is composed of preamplifier, Sigma-Delta ADC, DSP and Sigma-Delta DAC with low-power technique. The hardwired DSP has 6 parameters to reduce power consumption with high flexibility. The Sigma-Delta DAC adopts heterogeneous frequency to reduce power consumption further. The proposed digital hearing aid chip achieves 79-dB peak SNR and dissipates 96-muW from a single 0.9-V supply. The core area is 2.7-mm
²
in a 0.18-mum standard CMOS technology