A Digital PLL with a Stochastic Time-to-Digital Converter

A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13mum CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz