A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

This paper proposes a voltage-control scheme for an SRAM that makes a minimum operation voltage down to 0.3 V even on a future memory-rich SoC. A self-aligned timing control guarantees stable operation in a wide range of Vdd under DVS environment. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that 30% power reduction is achieved at 100 MHz. The area overhead is only 5.6%