A 3.2Gb/s Semi-Blind-Oversampling CDR

A hybrid CDR increases jitter tolerance of a phase-tracking CDR by a factor of 32 at low frequencies, while maintaining the high-frequency jitter tolerance of a 5times blind-oversampling CDR. Measurements on a 0.11 μm CMOS test chip at 2.4Gb/s confirm a 200Ul
_pp
jitter tolerance at 200kHz. At 2.4Gb/s, the chip consumes 180mW from a 1.2V supply