A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm
²
die with an effective cell-size of 0.7191mum
²
while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst