A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control

A multi-rate transceiver incorporating TX slew control with >2times range, PLL with <0.5times loop-filter area using capacitance multiplication, and Δ ΣZ-SSCG having 11.7dB peak reduction is designed in 0.13mum CMOS. Occupying 2.33mm
²
with TX operable up to 8.5Gb/s, the quad transceiver consumes 386mW from 1.2V supply and has a BER<10
^-14
at 6Gb/s over an 8m cable with 22dB loss