Routing algorithms: architecture driven rerouting enhancement for FPGAs

The routing channels of today's FPGAs consist of wire segments of various types, which allow the use of new techniques to enhance the routability of net segments in channels. In this paper we present an optimal greedy algorithm to switch the tracks that net segments are assigned to. This allows us to enhance the rerouting ability by capturing the features of the routing architecture. Suppose the number of tracks in the channels is given. The goal of this algorithm is to increase the number of routed segments of late rerouting requests. This is a good feature for supporting engineering change order (ECO) type of routing. Supporting ECO routing enables the routing algorithms to deal with later changes in routing requests. We used the routing architecture of VirtexII FPGAs from Xilinx as our target architecture and integrated our algorithm into the VPR FPGA routing tool. The experimental results show that our algorithm makes VPR router capable of handling 28.4% more rerouting for segments that are added to the design later