A low-distortion fourth-order bandpass delta-sigma modulator

In this paper, a low-distortion fourth-order bandpass /spl Delta//spl Sigma/ modulator is proposed. The architecture of the modulator is based on the low-distortion /spl Delta//spl Sigma/ modulator. The analysis of the modulator due to the nonideal effect of the opamp and the capacitor mismatch is given, and the system-level simulation is provided to compare the performance to that of the traditional architecture. The modulator is implemented with a 0.35/spl mu/m CMOS process. A double-sampled technique is employed to relax the speed requirement of the opamp. The measured SNR (-3dBFS) is 47.8dB for a center frequency of 5 MHz and the signal bandwidth of 200 kHz at a clock frequency of 10 MHz (equivalent sampling frequency of 20 MHz).