Quantization noise reduction using multiphase PLLs

A 120 MHz fractional-N frequency synthesizer was implemented in a standard 0.18mum CMOS process with an on-chip multiphase voltage-controlled oscillator (VCO). The proposed architecture uses multiphase outputs of the VCO to decrease quantization noise from the sigma-delta (SigmaDelta) modulator. Results show the decrease in quantization noise from the 4th order SigmaDelta is 6dB for every two fold increase in the number of phases. The VCO phase noise was measured to be -104 dBc/Hz at 200 kHz offset. The loop bandwidth can be increased to 700 kHz and still maintain in-band quantization noise below -200 dBc/Hz. The power consumption of the synthesizer is 5.4 mW with a 1.8 V supply and it occupies an active area of 750 mum times 550 mum. The intended application is subharmonic injection higher frequency VCO and as a clock generator in a subsampling analog-to-digital converter (ADC)