Analysis of the Substrate Noise Effects due to DC-DC Converter Integration

Substrate noise mechanisms caused by the integration of a DC-DC converter into a 0.13 μm CMOS technology integrated circuit are investigated in order to provide designers with guidelines to improve sensitive analog/RF circuits isolation. In particular, the effects of the DRIFTMOS technological process and the dependence of substrate noise coupling on physical separation distance, floorplanning and introduction of guarding structures are fully described.