Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60 mW in a 0.25 /spl mu/m CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42 mW) and the isomorphic architecture (1.54 mW), without overly large area overhead (0.77 mm/sup 2/ against 0.43 mm/sup 2/ and 4.31 mm/sup 2/, respectively).