Practical aspects of reliability analysis for IC designs

Voltage analysis is a major part of design-in reliability as voltage is the driver for electric degradation in dielectrics and MOS devices. Particularly, voltage has the largest influence on gate oxide reliability. An important trend designers should be aware of is the planned shift to new gate oxide failure criteria, which will tolerate progressive soft breakdowns in the gate oxide introducing additional gate leakage and noise. With increasing electric oxide fields negative bias instability of pFET devices became a severe problem, which cannot be solved by technology alone but requires also design solutions. Thus, simulation of MOSFETs being degraded by hot carrier stress and negative bias temperature stress becomes mandatory, as well as the control of device properties of circuit elements in a design. Design-in reliability in the metallization levels mainly is related to via placing and therefore, design tools should be able to trade off between increase in size, e.g. due to redundant vias, and benefit in reliability. Analysis of metal lines with maximum potential difference and minimal spacing also becomes mandatory in order to calculate the risk of time-dependent dielectric breakdown in the inter-metal dielectric, particularly for low-k dielectrics. From ESD point of view the following demands exist for future EDA solutions: 1) verification of net oriented ESD rules, 2) IR-drop analysis on layout to check ESD metallization rules, and 3) automatic placement of ESD or I/O cells depending on some formalized ESD guide lines that codify the ESD protection concept.