Reliability challenges for 45nm and beyond

Scaling, for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits. This requires that designers have to be very careful with: high current densities, voltage overshoots, and localized hot spots on the chip, high duty-cycle applications, and high thermal-resistance packaging. In addition to the reliability issues, interconnect RC time-delay worsen with scaling because Cu resistivity is expected to increase due to surface and grain boundary scattering in very narrow interconnects. Also, the low-k interconnect-dielectric introduction rate has been much slower than ITRS roadmap forecasts.