Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

In this paper we propose a novel projection-based algorithm to estimate the full-chip leakage power with consideration of both inter-die and intra-die process variations. Unlike many traditional approaches that rely on log-normal approximations, the proposed algorithm applies a novel projection method to extract a low-rank quadratic model of the logarithm of the full-chip leakage current and, therefore, is not limited to log-normal distributions. By exploring the underlying sparse structure of the problem, an efficient algorithm is developed to extract the non-log-normal leakage distribution with linear computational complexity in circuit size. In addition, an incremental analysis algorithm is proposed to quickly update the leakage distribution after changes to a circuit are made. Our numerical examples in a commercial 90nm CMOS process demonstrate that the proposed algorithm provides 4/spl times/error reduction compared with the previously proposed log-normal approximations, while achieving orders of magnitude more efficiency than a Monte Carlo analysis with 104 samples.