Towards a C++-based design methodology facilitating sequential equivalence checking

It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of systems-on-chip (SoC). These models are written in C++ primarily because it is possible to achieve very high simulation speeds, but also because it is productive to code at high levels of abstraction. In this paper we present a modeling methodology that continues to exploit the inherent advantages of writing models in C++ while ensuring that they are usable for formal verification of RTL through the use of sequential equivalence checking technology. An industrial case study is presented to show the validity of the approach.