A regenerative comparator structure with integrated inductors

We employ on-chip inductors to improve the sampling speed and power consumption of regenerative comparators. Since these inductors are far smaller than those used in typical RF designs, the addition of inductors has little impact on area. Simulations based on accurate inductor models indicate more than a doubling of comparator sampling speed for a given power consumption, or a halving in power consumption for a given sampling speed. We present a detailed analysis of the new scheme. The technique is verified with test measurements of 16 comparators, implemented in 0.18-/spl mu/m digital CMOS, sampling at 3.84 GHz.