A Balanced Pipelining Approach to Multiprocessing on an Instruction Stream Level

This paper presents an approach to achieve high central processing unit (CPU) availability with an increase in performance by multiprocessing on an instruction stream level, where instruction fetching/executing is done by closely coupled processing units (PU's). A treatment is given of the necessary control for coordination of the PU's. This processing interaction is accomplished by microcode shared by the units. Either PU can be interchanged in any processing function, and the total processing complex comprises a single CPU as far as the external world (i. e., the operating system and user's programs) is concerned. The results of manual simulation on two sample problems are given along with a comparison of processing with a single PU and with another instruction stream multiprocessing scheme presented in [4].