Efficient deterministic test generation for BIST schemes with LFSR reseeding

We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses binary decision diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes