The Implementation of a High Speed Adaptive FIR Filter on a Field Programmable Gate Array

Adaptive filters have become a very useful building block in several of today's systems. One of the most common application being line echo cancellation (LEC). The ever increasing data rates used in such communication systems bring along the need for faster adaptive filtering systems that are capable of handling the echo tail generated. This poses two main requirements, i) robust and stable algorithms to ensure efficient functionality under these conditions and ii) more processing power. This paper describes the implementation of such an adaptive filter on a Xilinx Spartan 3 FPGA for use in an echo cancellation system