Capacitance Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-K Gate Dielectric Considering Gate Tunneling Leakage Current

This paper reports the C
_SG
/C
_DG
capacitance behavior of 100 nm fully-depleted (FD) SOI CMOS devices with HfO
₂
high-k gate dielectric considering gate tunneling leakage current. According to the 2D simulation results, a unique two-step C
_SG
/C
_DG
versus V
_G
curve exists for the device with the 1.5 nm HfO
₂
gate dielectric due to the vertical displacement effect. Gate tunneling leakage current has a more impact on C
_DG
as compared to C
_SG