Device Integration Issues Towards 10 nm MOSFETs

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high kappa gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO
₂
/Al
₂
O
₃
. Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated. Finally ultra thin body SOI devices with high mobility SiGe channels are demonstrated